1. Field of the Invention
This invention relates to a process for fabricating a Schottky-barrier gate field effect transistor.
2. Description of the Prior Art
Schottky-barrier gate field effect transistors (which will hereinafter be referred to as "MESFETS") have widely been used as an element for amplification or oscillation, in particular, in microwaves, and as well known in the art, are excellent as a basic element for an integrated circuit of ultra-high speed operation.
The structure of the most commonly used MESFET is as shown in FIG. 1, in which 1 is a high resistance or semi-insulating semiconductor crystal substrate, 2 is an electrically conductive semiconductor crystal layer generally called an active layer, 3 is a Schottky-barrier gate electrode and 4 and 5 are respectively a source electrode and drain electrode having ohmic characteristics. The carrier concentration Nd and thickness a of the active layer 2 have a relationship with the pinch-off voltage Vp of MESFET, represented by the following formula (1): EQU Vp=Vb[(qNd)/2.epsilon.]a.sup.2 ( 1)
where Vb is a built-in voltage, .epsilon. is a dielectric constant of the semiconductor and q is an electronic charge.
Vp is given from the requirements of a circuit design and Nd and a are determined useing the formula (1) so as to satisfy the value of Vp.
One disadvantage of the prior art structure as shown in FIG. 1 is that the transconductance gm obtained is not sufficiently large and the noise characteristic is deteriorated, because the resistance between gate 3 and source 4 or gate 3 and drain 5 is high. In particular, where the absolute value of the pinch-off voltage Vp is small or in the case of "normally off" (Vp&gt;0), Nd- and a-values should be small and thus the series resistance between a gate and source is larger as is evident from the formula (1). When active layer 2 is of a GaAs crystal, there is a high density surface state on crystal surface areas 6 and 7 between a gate and source and between a gate and drain, whereby the surface potential is substantially fixed and a depletion layer is formed near the surface of the semiconductor crystal, resulting in a larger series resistance between a gate and source. This is a very important problem.
As a method of solving this problem, it has hitherto been proposed to make thicker active layers 9 and 10 between a gate and source and between a gate and drain than active layer 8 directly under the gate, as shown in FIG. 2. According to this method, however, it is required to determine the thickness of active layer 8 and the carrier concentration so as to satisfy the condition of the formula (1), but it is difficult to control precisely and reproducibly the thickness of the part 8 in such a recess structure by etching and the like in view of the present technical level. This structure is obtained by forming a uniform active layer having a thickness desired for the portion directly under source electride 4 and drain electrode 5, making thinner only part 8 to be directly under gate electrode 3 by etching and the like and then forming electrodes 4, 5 and 3. However, this structure has the disadvantage that not only a fine photolithography for forming an electrode is difficult, but also a much higher precision is required for etching control of an active layer thus resulting in a lowered yield, because the surface of the active layer is not flat.